Solid state imaging devices, including charge coupled devices (CCD), complementary metal oxide semiconductor (CMOS) imaging devices, and others, have been used in photo imaging applications. A solid state imaging device circuit includes a focal plane array of pixels as an image sensor, each pixel including a photosensor, which may be a photogate, a photoconductor, a photodiode, or other photosensor having a doped region for accumulating photo-generated charge. For CMOS imaging devices, each pixel has a charge storage region, formed on or in the substrate, which is connected to the gate of an output transistor that is part of a readout circuit. The charge storage region may be constructed as a floating diffusion region. In some CMOS imaging devices, each pixel may further include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level.
In a CMOS imaging device, the active elements of a pixel perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state; (4) transfer of charge to the storage region; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
A conventional four transistor (4T) CMOS image sensor pixel 100 is shown in FIG. 1. The pixel 100 includes a photosensor 102 (e.g., photodiode, photogate, etc.), transfer transistor 104 (having a gate 104a), floating diffusion region FD, reset transistor 106 (having a gate 106a), source follower transistor 110 (having a gate 110a), and row select transistor 112 (having a gate 112a). The photosensor 102 is connected to the floating diffusion region FD by the transfer transistor 104 when the gate 104a is activated by a transfer control signal TX.
The reset transistor 106 is connected between the floating diffusion region FD and a voltage supply line 206. A reset control signal RST is applied to reset transistor gate 106a to activate the reset transistor 106, which resets the floating diffusion region FD to the voltage supply line 206 level as is known in the art.
The source follower transistor 110 is connected between the voltage supply line 206 and the row select transistor 112. Source follower transistor gate 110a is connected to the floating diffusion region FD. The source follower transistor 110 converts the charge stored at the floating diffusion region FD into an electrical output voltage signal Vout. The row select transistor 112 is controllable by gate 112a (activated by a row select signal ROW) for selectively connecting the source follower transistor 110 and its output voltage signal Vout to a column line of a pixel array.
In order to capture images with greater resolution while also maintaining a small image sensor size, it is desirable to design image sensors with a large number of relatively small pixels. Unfortunately, as pixels 100 become smaller, many of the transistors responsible for reading out pixel signals, such as transistors 106, 110, and 112 in FIG. 1, cannot be made smaller and begin to take up most of the space allocated to each pixel 100. Consequently, the photosensor 102 becomes smaller while more of the pixel area is used by the pixel transistors, such that, the pixel's 100 fill factor, which is the percentage of a pixel that is photosensitive, is reduced. As photosensor size and pixel fill factor shrink, the amount of light that is converted to a signal within each pixel decreases as well. Accordingly, there is a need for a pixel architecture that allows for smaller pixels with higher fill factors. There is also a need for a pixel architecture that can operate at high speed as pixel density increases.